# Adders, Multiplexers, and Decoders

Computer Science I · Basic Digital Design · https://tryals.app/learn/computer-science-i/adders-multiplexers-and-decoders

## Building Blocks: Adders

Instead of raw gates, engineers use **standard building blocks**: reliable combinational modules acting like Lego pieces.

The **half adder** adds two bits to output a **sum** ($A \oplus B$) and a **carry** ($A \cdot B$). A **full adder** adds three bits including a **carry-in**, outputting a sum and **carry-out**.

Chaining $n$ full adders builds a **ripple-carry adder** for $n$-bit numbers. Wider numbers take longer because the carry must ripple through every stage.

## MUX vs. Decoder

A **multiplexer (MUX)** is a data selector routing one of $2^k$ inputs to a single output using $k$ **select** lines ($2^k \text{ inputs} \Rightarrow k \text{ select lines}$). It acts as hardware if/else.

A **decoder** does the opposite: a $k$-bit input activates exactly one of $2^k$ outputs. Its inverse is an **encoder**.

| Block | Structure | Function |
| --- | --- | --- |
| **MUX** | Many inputs, 1 output | Routes chosen data |
| **Decoder** | $k$ inputs, $2^k$ outputs | Activates one line |

> **Common pitfall:** MUXes narrow many inputs to one; decoders fan a small input out to many outputs.

## Practice questions

3 of this lesson's 10 practice questions, with answers. The full set is in the app.

### 1. Order what happens when a four-bit ripple-carry adder computes a sum.

**Answer:**

1. The rightmost stage adds the two least significant bits together with the incoming carry
2. Its carry-out arrives at the carry-in of the stage to its left
3. That stage can now settle and produce its own sum bit and carry-out
4. The carry travels left through each remaining stage in the same way
5. The carry-out of the leftmost stage becomes the adder's final carry

**Why:** Each stage needs its carry-in before it can settle, so the stages finish one after another from right to left rather than all at once. Assuming the stages work in parallel is exactly the misconception that makes ripple-carry delay surprising, the sum bits appear in sequence, not simultaneously.

Page: https://tryals.app/practice/computer-science-i/adders-multiplexers-and-decoders/order-what-happens-when-a-four-bit-ripple-carry-adder-computes-a-sum

### 2. A ripple-carry adder's delay grows with the number of bits because each stage waits for the carry from the one below it.

**Answer:** True

**Why:** True. The carry propagates serially, so a 64-bit ripple-carry adder is 64 gate delays deep and the adder sets the processor's critical path. Carry-lookahead computes the carries in parallel from generate and propagate signals, trading a great many more gates for logarithmic depth.

Page: https://tryals.app/practice/computer-science-i/adders-multiplexers-and-decoders/a-ripple-carry-adders-delay-grows-with-the-number-of-bits-because

### 3. A 64-bit ripple-carry adder is 64 gate delays deep and sits on the critical path of nearly every instruction. What does carry-lookahead buy, and what does it cost?

A. Delay growing like log n instead of n, at the cost of many more gates
B. Fewer gates, by sharing the carry computation across stages
C. Exact arithmetic, which ripple-carry cannot guarantee at 64 bits
D. Lower power, since the carry chain no longer toggles repeatedly

**Answer:** A. Delay growing like log n instead of n, at the cost of many more gates

**Why:** The carry chain is the bottleneck, and lookahead breaks it by computing each carry directly from the inputs rather than from its predecessor, logarithmic depth for a lot more silicon. It is the area-versus-speed trade in its purest form, which is why real adders are hierarchical compromises rather than either extreme.

Page: https://tryals.app/practice/computer-science-i/adders-multiplexers-and-decoders/a-64-bit-ripple-carry-adder-is-64-gate-delays-deep-and-sits-on-the