# Data Path and Control

Computer Science I · Introduction to Computers · https://tryals.app/learn/computer-science-i/data-path-and-control

## Wiring the Data Path

The CPU's **data path** is the network of registers, the ALU, and the **multiplexers** between them. The **control** logic sets the switches on this network so operands flow along the right route for every instruction.

Every CPU understands an **instruction set architecture (ISA)**. A machine instruction is a bit pattern split into fields:

| Field | Purpose | Example | Dimensions |
| --- | --- | --- | --- |
| **Opcode** | Selects the operation | ADD | Determines broad class |
| **Operand** | What the operation acts on | R1, R2 | Register or immediate |

Instructions fall into three families: **arithmetic/logic** (route operands into ALU), **data transfer** (load/store between register and memory), and **control flow** (jump/branch).

> **Common pitfall:** Conflating the **opcode** with the **operands**. "ADD R1, R2" has one opcode (ADD) and two operands (R1, R2). The opcode selects the operation; the operands feed it.

## Instruction Formats in RISC-V

RISC-V uses **32-bit** instructions with fixed field positions. An arithmetic instruction uses the **R-type** format:

- **opcode** (7 bits): broad class of instruction.
- **rd** (5 bits): destination register.
- **rs1** and **rs2** (5 bits each): source registers.
- **funct3** (3 bits) and **funct7** (7 bits): specific operation, like add or subtract.

Five bits addresses 32 registers ($2^{5} = 32$). The **I-type** format replaces rs2 and funct7 with a 12-bit **immediate** value.

RISC-V is a **load–store architecture**: arithmetic instructions touch only registers, and memory is reached solely via explicit load and store instructions.

> **Common pitfall:** Viewing fixed 32-bit width as waste. Fixed widths let the fetch unit always know where the next instruction begins, making hardware decoding fast and uniform.

## Practice questions

5 of this lesson's 12 practice questions, with answers. The full set is in the app.

### 1. The control unit works out what an instruction does by inspecting its operand fields.

**Answer:** False

**Why:** False. The **opcode** selects the operation and drives the control signals; the operand fields say only which registers or addresses to use. The split is what makes an instruction set a hardware contract, the encoding *is* the interface between compiler and processor.

Page: https://tryals.app/practice/computer-science-i/data-path-and-control/the-control-unit-works-out-what-an-instruction-does-by-inspecting-its

### 2. Modern x86 processors translate their own instructions into simpler internal micro-operations before executing them. Why build a chip that does not directly run its own instruction set?

A. Because the x86 instruction set is no longer documented
B. Because micro-operations execute faster than any instruction set could
C. Because a fixed internal format pipelines better than the legacy encoding
D. Because translation is required to support multiple cores

**Answer:** C. Because a fixed internal format pipelines better than the legacy encoding

**Why:** The instruction set is the promise and the microarchitecture is free to change, so decades of binaries keep working while the silicon underneath is redesigned repeatedly. It costs real transistors to decode, and the compatibility is worth more, which is abstraction earning its keep at the hardware level.

Page: https://tryals.app/practice/computer-science-i/data-path-and-control/modern-x86-processors-translate-their-own-instructions-into-simpler

### 3. The CPU is executing ADD R1, R2, writing the result back into R1. Select every control signal the control unit must produce for this instruction.

A. The main-memory address the result should be stored at
B. Whether the ALU should add or subtract
C. Which register the ALU's result is written back to
D. The new value to load into the program counter
E. Which registers to read onto the ALU's inputs

**Answer:** B. Whether the ALU should add or subtract; C. Which register the ALU's result is written back to; E. Which registers to read onto the ALU's inputs

**Why:** An arithmetic instruction needs its sources selected, the ALU's function chosen, and its destination selected, three signals along one route. It touches no memory address (that would be a data-transfer instruction) and sets no PC target (that would be control flow). Assuming every instruction touches memory is the trap.

Page: https://tryals.app/practice/computer-science-i/data-path-and-control/the-cpu-is-executing-add-r1-r2-writing-the-result-back-into-r1

### 4. Match each field of a 32-bit RISC-V instruction to what it selects.

**Answer:**

- opcode (7 bits) → The broad class the instruction belongs to
- rd (5 bits) → Where the outcome lands, chosen from 32 registers
- rs1 and rs2 (5 bits each) → Where the two inputs are read from
- funct3 and funct7 → Which operation within the class, such as add rather than subtract
- immediate (12 bits, I-type) → A constant carried inside the instruction itself

**Why:** The opcode names the class and funct3 with funct7 pick the exact operation inside it, which is why add and subtract share an opcode. Three separate 5-bit fields name registers, two sources and one destination, because 5 bits is exactly enough for 32 of them. The immediate exists only in formats that trade rs2 and funct7 away for a constant.

Page: https://tryals.app/practice/computer-science-i/data-path-and-control/match-each-field-of-a-32-bit-risc-v-instruction-to-what-it-selects

### 5. Two instructions are given: 'ADD R1, R2' adds two registers, and 'ADDI R3, 7' adds the constant 7 to a register. Sort each field by the role it plays.

**Answer:**

- Opcode: ADD, ADDI
- Register operand: R1, R2, R3
- Immediate operand: 7

**Why:** ADD and ADDI are opcodes, they select the operation. R1, R2 and R3 name registers to read from or write to. The 7 is an immediate: a constant baked into the instruction, needing no register read. Reading the opcode and operand fields in the wrong roles is the classic decoding mistake.

Page: https://tryals.app/practice/computer-science-i/data-path-and-control/two-instructions-are-given-add-r1-r2-adds-two-registers-and