# Flip-Flops and Registers

Computer Science I · Basic Digital Design · https://tryals.app/learn/computer-science-i/flip-flops-and-registers

## Flip-Flop Basics & Memory

A **flip-flop** is a one-bit memory element that changes state only on a clock **edge** (the instant the clock transitions from 0 to 1). This edge-triggering ensures predictable, once-per-tick updates, unlike a level-sensitive latch.

The **D flip-flop** ("data" flip-flop) is the most common type: on each clock edge, its output $Q$ takes the value of its input $D$. In short, it remembers whatever $D$ was at the tick.

| Feature | Latch | Flip-Flop |
| --- | --- | --- |
| **Sensitivity** | Level-sensitive | Edge-triggered |
| **Transparency** | Transparent when enabled | Samples only at clock edge |
| **Timing Risk** | High risk of timing bugs | Stable, predictable updates |

**Common pitfall:** Confusing an edge-triggered **flip-flop** with a level-sensitive **latch**. A latch lets outputs follow inputs continuously while active, causing subtle timing bugs if used where strict edge-sampling is required.

## Registers and Sequential Circuits

Wiring $n$ D flip-flops side by side, driven by the same clock, creates an **$n$-bit register**. This unit stores an $n$-bit value and updates all bits simultaneously on each clock edge.

Registers form the fast working storage inside a CPU. Feed a register's output back through combinational logic to build stateful machines:

* **Counter:** A register whose next value is current + 1, incrementing each tick.
* **Shift Register:** Moves its stored bits one position per tick.

All sequential circuits follow this core pattern: **flip-flops** hold the state, combinational logic computes the next state, and the clock advances it.

## Practice questions

3 of this lesson's 10 practice questions, with answers. The full set is in the app.

### 1. A level-sensitive latch is transparent while its enable is high; an edge-triggered flip-flop captures only at the instant of a clock edge. Why does synchronous design overwhelmingly use flip-flops?

A. Because transparency lets data race ahead through several stages.
B. Because flip-flops can store more than one bit while latches cannot.
C. Because latches cannot store a value once the enable signal is removed.
D. Because latches consume more power than flip-flops in every technology.

**Answer:** A. Because transparency lets data race ahead through several stages.

**Why:** While a latch is transparent its output follows its input, so a value can pass straight through it and through the next transparent stage too, data races forward by an unpredictable number of stages and the design depends on exact delays. A flip-flop samples once and holds, so data advances exactly one stage per clock, which is what makes timing analysis tractable.

Page: https://tryals.app/practice/computer-science-i/flip-flops-and-registers/a-level-sensitive-latch-is-transparent-while-its-enable-is-high-an

### 2. A shift register moves every bit one place per clock and is used for serial-to-parallel conversion. What problem is it solving?

A. Storing more data than a parallel register of the same width
B. Trading time for wires, one bit per clock accumulated into a word
C. Increasing the clock frequency of the receiving circuit
D. Error detection, by checking bits as they arrive

**Answer:** B. Trading time for wires, one bit per clock accumulated into a word

**Why:** Pins and board traces are expensive, so serial links send bits over time and the shift register reassembles them into a word, time traded for wires. It is why USB, SATA and PCIe are serial despite sounding slower, and why every one of them has a shift register at each end.

Page: https://tryals.app/practice/computer-science-i/flip-flops-and-registers/a-shift-register-moves-every-bit-one-place-per-clock-and-is-used-for

### 3. A two-bit counter holds 00 and increments on every clock edge, wrapping after its largest value. Order the values it holds after the next four edges.

**Answer:**

1. 01
2. 10
3. 11
4. 00

**Why:** 00 becomes 01, then 10, then 11, then wraps to 00 after four edges, a two-bit counter has a period of four. Expecting 100 after 11 is the fixed-width slip; the carry out of the top bit has nowhere to go and is discarded.

Page: https://tryals.app/practice/computer-science-i/flip-flops-and-registers/a-two-bit-counter-holds-00-and-increments-on-every-clock-edge