# Integrated Computer-System Reasoning

Computer Science I · Introduction to Computers · https://tryals.app/learn/computer-science-i/integrated-computer-system-reasoning

## The Whole Machine at Once

Study parts separately, but reason about the **whole system**. Take a simple job: read a key, add one, and store it. 

* **I/O Event**: The keypress arrives via interrupt.
* **Encoding**: It is stored as bits in memory.
* **Execution**: The CPU fetches via cache, and the **ALU** adds.

Every layer of the course appears in one task. **Abstractions** hide internal complexity behind clean interfaces, letting programmers work at one level while knowing lower layers exist for performance tuning.

## Finding the Bottleneck

System performance is governed by its **bottleneck**: the slowest stage that work must pass through. Speeding up a non-bottleneck yields little.

| Layer Type | Speed Relative to CPU |
| --- | --- |
| Registers | Fastest (Base) |
| Cache / Main Memory | Moderate to Slow |
| Disk / I/O | Millions of times slower |

> **Common pitfall:** Optimizing the wrong layer. Making CPU arithmetic faster helps nothing if the task is waiting on **I/O** or a **cache miss**.

## Practice questions

5 of this lesson's 11 practice questions, with answers. The full set is in the app.

### 1. Match each layer or idea to its role in the whole machine.

**Answer:**

- Encoding layer → Decides what a given bit pattern means
- Data path → Routes operands to the ALU and results back
- Memory hierarchy → Trades size against speed across several layers
- Bottleneck → The slowest stage the work must pass through

**Why:** Encoding governs meaning, the data path governs movement within the CPU, the hierarchy governs the size-versus-speed trade, and the bottleneck is the property of a particular workload that decides where optimisation is worth doing at all.

Page: https://tryals.app/practice/computer-science-i/integrated-computer-system-reasoning/match-each-layer-or-idea-to-its-role-in-the-whole-machine

### 2. Order the stages of the task 'read a number from the keyboard, add one, and store the result' as the information flows through the machine.

**Answer:**

1. A keypress arrives as an I/O event and raises an interrupt
2. The character is encoded as bits and placed in main memory
3. The CPU fetches the add instruction, checking the cache first
4. The ALU performs the addition inside the data path
5. The result is stored back to main memory

**Why:** Every layer of the course appears once, in order: I/O, encoding, the memory hierarchy, the data path and ALU, then memory again. Expecting the addition before the fetch skips the fact that the add instruction is itself data that has to be brought in.

Page: https://tryals.app/practice/computer-science-i/integrated-computer-system-reasoning/order-the-stages-of-the-task-read-a-number-from-the-keyboard-add

### 3. Select every statement that the bottleneck principle actually supports.

A. You should measure where time is spent before optimising
B. Doubling CPU speed on an I/O-bound task barely helps
C. A register access and a disk access differ by only a small factor
D. Speeding up a stage that is not the bottleneck gives little overall gain
E. The bottleneck is always the CPU

**Answer:** A. You should measure where time is spent before optimising; B. Doubling CPU speed on an I/O-bound task barely helps; D. Speeding up a stage that is not the bottleneck gives little overall gain

**Why:** The principle says overall time is governed by the slowest stage, so improvements elsewhere barely register and measuring must come first. The layers differ by factors of millions, not a small factor, and the bottleneck is very often I/O or memory rather than the CPU, which is why option 5 inverts the lesson.

Page: https://tryals.app/practice/computer-science-i/integrated-computer-system-reasoning/select-every-statement-that-the-bottleneck-principle-actually

### 4. A Python programmer never thinks about voltage, and a chip designer never thinks about dictionaries. What makes that division of labour possible, and where does it leak?

A. The layers are fully independent, and any apparent leak is a bug
B. Compilers eliminate all lower-level concerns automatically
C. The division works only for high-level languages, not systems languages
D. Each layer hides the one below, and leaks where physical reality shows through

**Answer:** D. Each layer hides the one below, and leaks where physical reality shows through

**Why:** Interfaces hide detail well enough to work with and not perfectly. Cache behaviour surfaces as performance big-O does not predict, fixed word size as overflow, binary fractions as 0.1 + 0.2 ≠ 0.3, and knowing which abstractions leak, and where, is most of what separates a competent engineer from a fluent one.

Page: https://tryals.app/practice/computer-science-i/integrated-computer-system-reasoning/a-python-programmer-never-thinks-about-voltage-and-a-chip-designer

### 5. A high-level language statement becomes machine instructions, which become voltage changes in transistors. Why is describing a computer at several levels of abstraction necessary rather than merely convenient?

A. Because abstraction makes programs run faster by skipping unnecessary hardware detail.
B. Because each level is a separate machine, and they communicate over defined protocols.
C. Because the lower levels are too unreliable to be reasoned about directly.
D. Because no one can hold the whole system at once, so each level hides the last.

**Answer:** D. Because no one can hold the whole system at once, so each level hides the last.

**Why:** A line of Python may involve billions of transistor switchings, and the layered structure is what makes reasoning about that unnecessary. The independence runs both ways commercially, 1990s x86 programs run on today's chips because the instruction set is the contract. The abstractions leak, and knowing where is part of being good at this: cache behaviour, floating point, integer overflow.

Page: https://tryals.app/practice/computer-science-i/integrated-computer-system-reasoning/a-high-level-language-statement-becomes-machine-instructions-which