# Integrated Digital-System Reasoning

Computer Science I · Basic Digital Design · https://tryals.app/learn/computer-science-i/integrated-digital-system-reasoning

## Datapath and Control

Every digital system—from a simple counter to a CPU—shares the standard **datapath and control** architecture. 

- **Datapath**: Combinational logic plus registers that move and transform data.
- **Control**: A finite state machine that directs what the datapath does each cycle.

| Component | Type | Function |
| --- | --- | --- |
| **Register** | Sequential | Holds the current value |
| **Adder** | Combinational | Computes current + step |
| **Comparator** | Combinational | Tests if target is reached |
| **Control FSM** | Sequential | Directs states like _running_ and _done_ |

Every unit theme converges here: gates build blocks, minimization keeps them cheap, sequential logic holds state, and timing analysis limits the clock by the **critical path**.

## Composition and Pitfalls

Digital systems are built through **composition and abstraction**: gates form blocks, blocks form datapaths, and a control FSM sequences them. Each layer hides the one below, allowing us to build working computers from basic boolean values.

> **Common pitfall:** Trying to reason about a whole digital system at the individual-gate level.

Real design requires thinking in terms of **blocks** and their interfaces, not thousands of individual gates. Descend to the gate level only when a specific block or timing path demands optimization.

## Practice questions

3 of this lesson's 10 practice questions, with answers. The full set is in the app.

### 1. Order the levels of a digital system from the smallest building block up to the whole machine.

**Answer:**

1. Individual logic gates
2. Blocks such as adders, comparators and multiplexers
3. A datapath that moves and transforms data through those blocks
4. A control state machine that sequences the datapath cycle by cycle
5. The complete system, advancing under one clock

**Why:** Gates form blocks, blocks form a datapath, a control machine sequences that datapath, and the clock disciplines the whole. Each layer hides the one below, which is what lets a designer reason about registers and adders instead of thousands of gates, the pitfall this lesson names is descending to gate level when block level would do.

Page: https://tryals.app/practice/computer-science-i/integrated-digital-system-reasoning/order-the-levels-of-a-digital-system-from-the-smallest-building-block

### 2. A datapath is widened from 8 to 32 bits to handle larger values, and the maximum clock frequency drops. Why does a change about range affect speed?

A. Because 32-bit values require more memory accesses per operation
B. Because a wider adder has a longer carry chain, so the clock must slow
C. Because wider registers consume more power, which forces a lower frequency
D. Because the wider datapath needs more clock cycles per operation

**Answer:** B. Because a wider adder has a longer carry chain, so the clock must slow

**Why:** The carry must propagate across four times as many stages, so the critical path grows and the period must follow. Range and speed are coupled through the adder, which is why datapath width is an architectural decision rather than a detail, and why carry-lookahead exists to weaken the coupling.

Page: https://tryals.app/practice/computer-science-i/integrated-digital-system-reasoning/a-datapath-is-widened-from-8-to-32-bits-to-handle-larger-values-and

### 3. A datapath holds a value in a register, adds a step to it each clock, and displays the result - drawing on gates, adders, registers and timing at once. Why is understanding each piece separately insufficient to design the system?

A. Because each piece behaves differently when combined, invalidating its individual specification.
B. Because the pieces constrain each other: delay, width and settling time.
C. Because a datapath requires components beyond gates, adders and registers.
D. Because the pieces are manufactured by different processes and must be integrated physically.

**Answer:** B. Because the pieces constrain each other: delay, width and settling time.

**Why:** The pieces are correct individually and coupled in their requirements: widening the adder for a larger range lengthens the carry chain, which lengthens the critical path, which lowers the clock, so a decision about range has become a decision about speed. Which is why hardware design proceeds by iteration, since the critical path is a property of the whole rather than of any part.

Page: https://tryals.app/practice/computer-science-i/integrated-digital-system-reasoning/a-datapath-holds-a-value-in-a-register-adds-a-step-to-it-each-clock