# Sequential Logic and State

Computer Science I · Basic Digital Design · https://tryals.app/learn/computer-science-i/sequential-logic-and-state

## Circuits That Remember

Combinational circuits are memoryless, but a computer must remember. **Sequential logic** adds **state**, meaning the circuit's output depends on current inputs and stored past information.

Memory comes from **feedback**, wiring an output back to an input. A **latch** is the simplest memory element, storing one bit that can be _set_ to 1 or _reset_ to 0.

| Concept | Combinational | Sequential |
| --- | --- | --- |
| **Memory** | None | Uses feedback |
| **Timing** | Continuous | Clock-driven |
| **Output** | Inputs only | Inputs and state |

Real designs are **synchronous**, governed by a **clock** ticking at a fixed rate. State updates happen only at a clock **edge** (rising or falling transition).

## Finite State Machines

A **finite state machine (FSM)** consists of a set of states, plus rules to determine the _next_ state and outputs. Examples include traffic lights and CPUs.

$$\text{next state} = f(\text{state}, \text{input})$$

Here, $\text{state}$ is held by the **state register**, while combinational logic computes the next state.

> **Common pitfall:** Thinking a sequential circuit responds continuously. In synchronous designs, state changes only at **clock edges**, advancing one step per tick.

## Practice questions

4 of this lesson's 10 practice questions, with answers. The full set is in the app.

### 1. A state machine's next-state logic is combinational and its state register is sequential. Why does that split make the design analysable?

A. Because combinational logic is faster than sequential logic
B. Because it reduces the number of states required
C. Because the two parts can be manufactured separately
D. Because it isolates the memory into one clocked register

**Answer:** D. Because it isolates the memory into one clocked register

**Why:** Concentrating memory in one register leaves everything else memoryless and therefore truth-table analysable, the same reason software separates pure computation from mutable state. It is one architectural pattern appearing at two levels for identical reasons.

Page: https://tryals.app/practice/computer-science-i/sequential-logic-and-state/a-state-machines-next-state-logic-is-combinational-and-its-state

### 2. In a synchronous sequential circuit, sort each item by which part of the circuit supplies it.

**Answer:**

- Combinational logic → Where the machine should go next, given where it is and what its inputs say
- From the clock → The exact instant at which the state is allowed to change
- In the state register → Which of the machine's states it is sitting in right now

**Why:** The register stores where the machine is and keeps it steady between edges; the combinational logic calculates the next state and the outputs; the clock decides when the calculated value replaces the stored one. Collapsing the next-state logic into the register is the usual muddle, the register does no computing at all, it only remembers.

Page: https://tryals.app/practice/computer-science-i/sequential-logic-and-state/in-a-synchronous-sequential-circuit-sort-each-item-by-which-part-of

### 3. A synchronous circuit updates its state only on a clock edge, even though the combinational logic settles at different times across the circuit. Why is waiting for a clock better than letting each part update as soon as it is ready?

A. Because asynchronous circuits are impossible to build with current technology.
B. Because the clock makes the circuit faster than it would otherwise be.
C. Because signals arrive at different times and must be allowed to settle.
D. Because combinational logic cannot produce a stable output without a clock signal.

**Answer:** C. Because signals arrive at different times and must be allowed to settle.

**Why:** Combinational outputs do not settle simultaneously, so between an input change and the stable result the wires carry transients a register would capture as nonsense. The period is chosen to exceed the longest path. The cost is that everything waits for the slowest, which is why the critical path sets the frequency, asynchronous circuits exist but are far harder to verify.

Page: https://tryals.app/practice/computer-science-i/sequential-logic-and-state/a-synchronous-circuit-updates-its-state-only-on-a-clock-edge-even

### 4. A crossing controller has four states. After Red it goes to Red-and-amber, after Red-and-amber to Green, after Green to Amber, and after Amber back to Red. The machine is currently in Green. Order the next four states it enters.

**Answer:**

1. Amber
2. Red
3. Red and amber together
4. Green

**Why:** From Green the rules give Amber, then Red, then Red-and-amber, then Green again, the cycle closes after four ticks. Reading the rules in the order they are listed rather than following them from the given starting state is the trap; an FSM's behaviour depends on where it currently is, not on how the transitions happen to be written down.

Page: https://tryals.app/practice/computer-science-i/sequential-logic-and-state/a-crossing-controller-has-four-states-after-red-it-goes-to