# Timing, Hazards, and Reliability

Computer Science I · Basic Digital Design · https://tryals.app/learn/computer-science-i/timing-hazards-and-reliability

## Timing and Speed Limits

Real gates are not instantaneous. **Propagation delay** is the time for a gate input change to reach its output. The **critical path** is the longest delay path between registers, setting how fast the circuit runs.

Flip-flops require inputs stable before the **setup time** and after the **hold time**. The minimum **clock period** is:

$T_{clock} \ge t_{cq} + t_{critical\ path} + t_{setup}$

| Term | Meaning |
| --- | --- |
| $t_{cq}$ | Clock-to-Q delay |
| $t_{setup}$ | Setup time |

The **critical path bounds the maximum clock frequency**. Speeding up means shortening this path or **pipelining**.

## Hazards and Reliability

Timing creates two reliability hazards. A **glitch** is an unwanted brief output pulse caused by path delays. Sampling at the clock edge hides glitches. **Metastability** occurs when setup/hold is violated, causing an unstable in-between state.

| Hazard | Cause | Mitigation |
| --- | --- | --- |
| **Glitch** | Path delay skews | Clock edge sampling |
| **Metastability** | Setup/hold violation | Synchronizer FFs |

> **Common pitfall:** Raising the clock frequency past the **critical path** bound causes setup violations and wrong results.

## Practice questions

4 of this lesson's 10 practice questions, with answers. The full set is in the app.

### 1. Setup time requires data to be stable before a clock edge; hold time requires it to remain stable after. Why can a hold violation not be fixed by slowing the clock, when a setup violation can?

A. Because hold violations are caused by manufacturing defects rather than by design.
B. Because hold time is measured in different units from the clock period.
C. Because slowing the clock increases hold time proportionally, cancelling the benefit.
D. Because hold is a race within one cycle, unaffected by the period.

**Answer:** D. Because hold is a race within one cycle, unaffected by the period.

**Why:** A setup violation means the logic did not finish, so a longer period fixes it, which is why a chip failing timing can be sold at a lower frequency. Hold says the new data arrived so fast it corrupted the value still being captured, a race between two paths that the period does not touch. The fix is inserting delay, and a chip with a hold violation is broken at every frequency.

Page: https://tryals.app/practice/computer-science-i/timing-hazards-and-reliability/setup-time-requires-data-to-be-stable-before-a-clock-edge-hold-time

### 2. Order what happens to a signal travelling between two registers during a single clock period.

**Answer:**

1. A clock edge arrives at the launching flip-flop
2. After its clock-to-output delay the flip-flop presents the new value
3. The value propagates through the combinational logic between the registers
4. The value settles and must then stay stable for the capturing flip-flop's setup time
5. The next clock edge arrives and the capturing flip-flop takes the value

**Why:** The three delays happen in sequence inside one period, and the setup window sits at the very end, just before the capturing edge. That is why the constraint adds the three quantities rather than overlapping them: each one must finish before the next can begin.

Page: https://tryals.app/practice/computer-science-i/timing-hazards-and-reliability/order-what-happens-to-a-signal-travelling-between-two-registers

### 3. Synchronous design tolerates combinational glitches by sampling outputs only at discrete clock edges. Why does this architectural strategy fail when signals violate setup or hold times?

A. Glitches only occur on clock lines while timing faults affect data paths
B. Clock edges eliminate transient pulses but cannot filter asynchronous noise
C. Glitches cause logic delay while timing violations permanently burn gates
D. Glitches settle over time whereas bistable elements enter metastable states

**Answer:** D. Glitches settle over time whereas bistable elements enter metastable states

**Why:** Combinational hazards naturally resolve once all path delays elapse, making clock-edge sampling effective. However, violating setup or hold windows traps the internal feedback of a flip-flop in a non-deterministic balance, which pure edge sampling cannot prevent.

Page: https://tryals.app/practice/computer-science-i/timing-hazards-and-reliability/synchronous-design-tolerates-combinational-glitches-by-sampling

### 4. Raising a synchronous circuit's clock frequency past the point where the slowest path can settle does not make it faster, it makes it wrong.

**Answer:** True

**Why:** True. The clock period must exceed the longest combinational delay plus setup time. Shorten it beyond that and flip-flops latch values that have not settled, the circuit produces wrong answers, sometimes intermittently and temperature-dependently. Going faster means shortening the critical path, not the period.

Page: https://tryals.app/practice/computer-science-i/timing-hazards-and-reliability/raising-a-synchronous-circuits-clock-frequency-past-the-point-where