Practice question · Multiple choice
A combinational circuit's output momentarily flickers to the wrong value after its inputs change, then settles correctly. Why does a synchronous design tolerate this?
Hints
- Different paths through the logic have different delays. Ask what is on the output while they finish.
- The register samples at one instant. Which instant?
Show the answer
C. Because registers sample only after the glitch has resolved
Why
Unequal path delays make glitches inevitable, and synchronous design does not remove them, it arranges never to look during them. That is what the clock period buys, and it is why asynchronous design is so much harder: without a sampling instant, every transient is potentially observed.
Practise Combinational Circuit Design
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