A level-sensitive latch is transparent while its enable is high; an edge-triggered flip-flop captures only at the instant of a clock edge. Why does synchronous design overwhelmingly use flip-flops?

A. Because transparency lets data race ahead through several stages.

While a latch is transparent its output follows its input, so a value can pass straight through it and through the next transparent stage too, data races forward by an unpredictable number of stages and the design depends on exact delays. A flip-flop samples once and holds, so data advances exactly one stage per clock, which is what makes timing analysis tractable.