A synchronous circuit updates its state only on a clock edge, even though the combinational logic settles at different times across the circuit. Why is waiting for a clock better than letting each part update as soon as it is ready?

C. Because signals arrive at different times and must be allowed to settle.

Combinational outputs do not settle simultaneously, so between an input change and the stable result the wires carry transients a register would capture as nonsense. The period is chosen to exceed the longest path. The cost is that everything waits for the slowest, which is why the critical path sets the frequency, asynchronous circuits exist but are far harder to verify.