The Instruction Cycle
A CPU runs programs by repeating the fetch–decode–execute cycle billions of times per second.
| Step | What happens | Key register |
|---|---|---|
| Fetch | Read instruction at PC; advance PC | Program counter (PC) |
| Decode | Interpret the operation and operands | Instruction register (IR) |
| Execute | Perform the ALU operation or memory move | ALU / registers / memory |
During fetch, the PC holds the instruction address and advances immediately, assuming sequential flow: . A jump or branch instruction changes this by writing a new address into the PC: .
Common pitfall: thinking a branch skips the cycle or works by magic. Every instruction goes through fetch–decode–execute; a branch simply overwrites a PC value that was already advanced.
Following a Real Instruction
RISC-V is an open instruction set where every instruction is 32 bits wide. Let's trace add x5, x6, x7 (add registers x6 and x7, store in x5) sitting at PC address 200:
- Fetch: Memory at 200 is copied to the IR. The PC advances to 204.
- Decode: The control unit reads the operation and fetches values from registers x6 and x7.
- Execute: The ALU adds them.
- Write back: The sum is written into x5.
Notice when the PC advanced: during fetch, before decoding. Hardware assumes sequential flow. A taken branch corrects it later by overwriting that already-advanced value.
Common pitfall: picturing the PC incrementing at the end of the cycle. It advances during fetch, and control-flow instructions overwrite that pre-set value.