Wiring the Data Path
The CPU's data path is the network of registers, the ALU, and the multiplexers between them. The control logic sets the switches on this network so operands flow along the right route for every instruction.
Every CPU understands an instruction set architecture (ISA). A machine instruction is a bit pattern split into fields:
| Field | Purpose | Example | Dimensions |
|---|---|---|---|
| Opcode | Selects the operation | ADD | Determines broad class |
| Operand | What the operation acts on | R1, R2 | Register or immediate |
Instructions fall into three families: arithmetic/logic (route operands into ALU), data transfer (load/store between register and memory), and control flow (jump/branch).
Common pitfall: Conflating the opcode with the operands. "ADD R1, R2" has one opcode (ADD) and two operands (R1, R2). The opcode selects the operation; the operands feed it.
Instruction Formats in RISC-V
RISC-V uses 32-bit instructions with fixed field positions. An arithmetic instruction uses the R-type format:
- opcode (7 bits): broad class of instruction.
- rd (5 bits): destination register.
- rs1 and rs2 (5 bits each): source registers.
- funct3 (3 bits) and funct7 (7 bits): specific operation, like add or subtract.
Five bits addresses 32 registers (). The I-type format replaces rs2 and funct7 with a 12-bit immediate value.
RISC-V is a load–store architecture: arithmetic instructions touch only registers, and memory is reached solely via explicit load and store instructions.
Common pitfall: Viewing fixed 32-bit width as waste. Fixed widths let the fetch unit always know where the next instruction begins, making hardware decoding fast and uniform.