Describing, Not Drawing
Modern chips have billions of gates — no one draws them by hand. Instead, engineers write a hardware description language (HDL) such as Verilog or VHDL, describing what the hardware should do, and a tool called a synthesizer turns that description into an actual gate-level circuit. Learning to think in HDL terms is central to digital design.
An HDL description works at two levels. A structural description says how components are wired together — "this MUX's output connects to that register's input" — mirroring a schematic. A behavioral description instead says what the hardware should do — "on each clock edge, if reset, set count to 0, else count to count + 1" — leaving the synthesizer to work out the gates. Behavioral descriptions are far more productive; you specify intent and let the tool implement it.
The crucial mindset shift is that HDL is not sequential software. HDL statements describe hardware that all exists and operates in parallel — everything happens at once, on every clock edge, not line by line. An assignment in HDL creates a permanent connection or a register update, not a one-time step in a procedure. Beginners who read HDL like a program misunderstand it badly.
Synthesis maps the description to a specific technology's gates and cells, optimizing for area, speed, or power, then place-and-route decides where each cell sits and how wires connect. The designer works at the behavioral level; the tools handle the millions of low-level decisions — the same abstraction-layering seen throughout computing.
Common pitfall: reading a hardware description language like ordinary sequential code, where statements run one after another. HDL describes hardware that operates concurrently — all blocks act in parallel, on every clock edge. An HDL "assignment" is a persistent hardware connection or a clocked update, not a sequential instruction; missing this leads to fundamentally wrong designs.
Hardware You Can Change After It Is Built
A hardware description eventually has to become a physical circuit, and there are two destinations. An ASIC is fabricated as fixed silicon: the fastest option and the cheapest per unit in volume, but enormously expensive to set up — and a mistake means another fabrication run. A programmable device is manufactured as a general-purpose array whose function is set electrically after manufacture, and can be set again.
The dominant kind is the FPGA, the field-programmable gate array: a grid of small logic blocks embedded in a programmable interconnect. Each block is built around a lookup table — a tiny memory holding the output for every possible input combination, so a -input LUT can realise any Boolean function of inputs simply by storing its truth table, which takes bits. Beside the LUTs sit flip-flops for sequential logic, plus hard blocks for what LUTs do badly: memories, multipliers, clock management. Smaller, simpler devices built on the same idea are called CPLDs.
Getting a description onto one runs through a fixed pipeline. Synthesis turns the HDL into a netlist of gates and registers; technology mapping packs that netlist into the LUTs and flip-flops the device actually has; place and route decides which physical blocks are used and which wires join them; and the outcome is written out as a bitstream, loaded into the device's configuration memory.
Common pitfall: reading "programmable" as "runs a program". Nothing is executed step by step — configuring an FPGA rewires it, and the resulting logic then runs in parallel like any other circuit. Its speed is governed by the propagation delay through the placed logic, not by a count of instructions.