Describing Hardware
Modern chips are too complex to draw by hand. Engineers write a hardware description language (HDL), describing what the hardware should do, and a synthesizer turns it into gates. HDL is not sequential software. Everything operates in parallel: statements describe permanent connections or clocked updates, not lines running one after another.
| Style | What it specifies | Analogy |
|---|---|---|
| Structural | How components are wired | Schematic |
| Behavioral | What the hardware should do | Intent |
Common pitfall: Reading HDL like a program. Missing that hardware runs concurrently leads to fundamentally broken designs.
ASICs and FPGAs
Designs target two physical destinations. An ASIC is fixed silicon: fast and cheap at volume, but costly to design. A programmable device is set electrically after manufacture. The FPGA (field-programmable gate array) features a grid of logic blocks and programmable interconnect.
Logic blocks center on the lookup table (LUT): a tiny memory holding the output for every input combination. A -input LUT realizes any Boolean function using bits.
| Stage | What it does |
|---|---|
| Synthesis | Turns HDL into a gate netlist |
| Tech Mapping | Packs netlist into actual LUTs/flip-flops |
| Place & Route | Assigns physical blocks and wires |
Common pitfall: Thinking "programmable" means "runs a program". FPGAs are rewired, not executed step-by-step.