Why Circuits Have Speed Limits
Real gates are not instantaneous. Propagation delay is the time for a change at a gate's input to appear at its output. Signals travel through chains of gates, so the delay accumulates along a path; the critical path — the longest delay path between registers — sets how fast the whole circuit can run.
Flip-flops impose timing requirements around the clock edge. The input must be stable for a short window before the edge (the setup time) and after it (the hold time); violate either and the flip-flop may capture a wrong or unstable value. Combining these gives the fundamental limit: the clock period must be long enough for a signal to leave one register, propagate through the worst-case combinational path, and satisfy the next register's setup time. That is:
So the critical path bounds the maximum clock frequency — you cannot clock a circuit faster than its slowest path allows. Speeding a circuit up means shortening that path (fewer gates in series, or pipelining to break it into shorter stages).
Two reliability hazards arise from timing. A glitch (hazard) is a brief, unwanted output pulse when signals along different paths arrive at slightly different times; in synchronous designs, sampling only at the clock edge (after signals settle) hides glitches. Metastability is a deeper danger: if a flip-flop's setup/hold is violated (often by an input from another, unsynchronized clock domain), it can enter an unstable in-between state for an unpredictable time — mitigated, never fully eliminated, by synchronizer flip-flops.
Common pitfall: assuming a circuit can be clocked arbitrarily fast just by raising the clock frequency. The clock period is bounded below by the critical path delay plus setup time — clock faster than that and signals will not have settled, causing setup violations and wrong results. To go faster you must shorten the critical path, not merely crank the clock.