Timing, Hazards, and Reliability

Timing and Speed Limits

Real gates are not instantaneous. Propagation delay is the time for a gate input change to reach its output. The critical path is the longest delay path between registers, setting how fast the circuit runs.

Flip-flops require inputs stable before the setup time and after the hold time. The minimum clock period is:

$T_{clock} \ge t_{cq} + t_{critical\ path} + t_{setup}$

The critical path bounds the maximum clock frequency. Speeding up means shortening this path or pipelining.

Hazards and Reliability

Timing creates two reliability hazards. A glitch is an unwanted brief output pulse caused by path delays. Sampling at the clock edge hides glitches. Metastability occurs when setup/hold is violated, causing an unstable in-between state.

Common pitfall: Raising the clock frequency past the critical path bound causes setup violations and wrong results.