Practice question · Put in order
Order what happens to a signal travelling between two registers during a single clock period.
- The value settles and must then stay stable for the capturing flip-flop's setup time
- The next clock edge arrives and the capturing flip-flop takes the value
- A clock edge arrives at the launching flip-flop
- After its clock-to-output delay the flip-flop presents the new value
- The value propagates through the combinational logic between the registers
Hints
- Nothing moves until an edge launches it, and nothing is stored until the following edge.
- The setup requirement is about the stretch of time just before the capturing edge, so it comes last of the delays.
Show the answer
- A clock edge arrives at the launching flip-flop
- After its clock-to-output delay the flip-flop presents the new value
- The value propagates through the combinational logic between the registers
- The value settles and must then stay stable for the capturing flip-flop's setup time
- The next clock edge arrives and the capturing flip-flop takes the value
Why
The three delays happen in sequence inside one period, and the setup window sits at the very end, just before the capturing edge. That is why the constraint adds the three quantities rather than overlapping them: each one must finish before the next can begin.
Practise Timing, Hazards, and Reliability
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