Practice question · Multiple choice
Synchronous design tolerates combinational glitches by sampling outputs only at discrete clock edges. Why does this architectural strategy fail when signals violate setup or hold times?
Hints
- What physical difference exists between transient gate skews and an unresolved flip-flop feedback state?
- Does waiting for a clock edge guarantee that a storage element itself will resolve to a clean logic level?
Show the answer
D. Glitches settle over time whereas bistable elements enter metastable states
Why
Combinational hazards naturally resolve once all path delays elapse, making clock-edge sampling effective. However, violating setup or hold windows traps the internal feedback of a flip-flop in a non-deterministic balance, which pure edge sampling cannot prevent.
Practise Timing, Hazards, and Reliability
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