Setup time requires data to be stable before a clock edge; hold time requires it to remain stable after. Why can a hold violation not be fixed by slowing the clock, when a setup violation can?

D. Because hold is a race within one cycle, unaffected by the period.

A setup violation means the logic did not finish, so a longer period fixes it, which is why a chip failing timing can be sold at a lower frequency. Hold says the new data arrived so fast it corrupted the value still being captured, a race between two paths that the period does not touch. The fix is inserting delay, and a chip with a hold violation is broken at every frequency.