Practice question · True or false
Raising a synchronous circuit's clock frequency past the point where the slowest path can settle does not make it faster, it makes it wrong.
Hints
- What is the clock period actually guaranteeing?
- A signal read before it settles is read at the wrong value.
Show the answer
True
Why
True. The clock period must exceed the longest combinational delay plus setup time. Shorten it beyond that and flip-flops latch values that have not settled, the circuit produces wrong answers, sometimes intermittently and temperature-dependently. Going faster means shortening the critical path, not the period.
Practise Timing, Hazards, and Reliability
The app has 6 more questions on this lesson, and keeps your place in the course. Computer Science I is free to start.
More questions on Timing, Hazards, and Reliability
- Setup time requires data to be stable before a clock edge; hold time requires it to remain stable after. Why…
- Order what happens to a signal travelling between two registers during a single clock period.
- Synchronous design tolerates combinational glitches by sampling outputs only at discrete clock edges. Why…